Charge sensitive amplifiers play an important role in imaging systems due to the low capacity of the subject signals in terms of current, i.e., charge, and duty cycle. For example, in large area, flat panel imaging systems, such as imaging systems for medical and document imaging applications based upon amorphous silicon, the image sensor is typically arranged as an array of pixels, each of which consists of a photo sensitive element and a thin film transistor (TFT).
In order achieve imaging frame rates suitable for video processing and display, all gate and data line connections for the sensor are brought out to the edge of the array for connection to an off-array control circuit containing row selection and charge sensing circuitry. As the resolution of such an array increases, more pixels become necessary for each data line, with the result being less signal capacity for each pixel. Further, as the number of pixels increases for a given active sensor area, the total parasitic capacitance on each data line increases since the size of each TFT is dictated by the rate at which the imaging information is read out, or sampled, from the array, and therefore, cannot generally be scaled linearly in accordance with the pixel pitch.
In fluoroscopic imaging, the signal levels associated with the minimum dose rate may be as low as 600 electrons, while the parasitic capacitance of each data line is approximately 100 picofarads. Under these circumstances, the difficulty for any charge sensitive amplifier connected to such a data line is to limit both the 1/f and thermal noise components of the amplifier and the input-referred power supply noise to a value less than one microvolt.
A conventional strategy for limiting charge sensitive amplifier noise is to use a single sided architecture with a large p-channel metal oxide semiconductor field effect transistor (P-MOSFET) as the input device. This single sided architecture can reduce the amplifier noise by a factor as great as the square root of two.
For many applications, the biggest noise problem related to the power supply involves power supply noise from on-chip digital switching circuits. In large area imaging, the pixels require biasing which is coupled, at least capacitively if not directly, to the data lines. Hence, the noise on the power supplies which bias the array is directly coupled to the input of the charge sensitive amplifiers which are connected to the data lines. Since limiting the power supply noise to a value of one microvolt RMS is a very difficult task, it is necessary to somehow reject the power supply noise injected at the input. Unfortunately, the ideal structure for rejecting this noise is a differential input amplifier which requires a second P-MOSFET, thereby increasing the amplifier noise across the parasitic data line capacitance by a factor of at least the square root of two.
Accordingly, it would be desirable to have a charge sensitive amplifier which is capable of rejecting power supply noise without increasing its own amplifier noise.